1. Technical Field
Embodiments described herein relate to a semiconductor package and a method of manufacturing the semiconductor package.
2. Related Art
With the recent increase in the performance of electronic equipment using semiconductor devices such as semiconductor chips, it is now required to, for example, increase the density of semiconductor chips in mounting them on a wiring board and miniaturize semiconductor packages incorporating semiconductor chips (space saving).
To this end, various structures have been proposed for what is called the POP (package on package) semiconductor package in which plural semiconductor chips are stacked on a wiring board. Various techniques have also been proposed for the manufacturing method of the POP semiconductor package.
However, in the POP semiconductor package, the external size of the semiconductor chip needs to be decreased gradually as its stacking position goes higher. That is, there is a problem in that the external dimensions of semiconductor chips to be stacked are restricted.
A semiconductor package 100 shown in FIG. 6 and its manufacturing method have been proposed for solving the above problem (see e.g., JP-A-2002-184936). More specifically, the semiconductor package 100 is a semiconductor device in which a first LSI chip 104 is mounted on a circuit board 103 and a larger, second LSI chip 106 is mounted on the first LSI chip 104. Underfill 110 that fills the space between the first LSI chip 104 and the circuit board 103 projects from the outer periphery and the top surface of the projected portion of the underfill is flush with that of the first LSI chip 104. In this manner, a base for receiving the bottom surface of the larger, second LSI chip 106 is formed to enable stable mounting of the second LSI chip 106. The restrictions relating to the chip external dimensions can be relaxed, and the semiconductor package 100 can be produced stably and is given high reliability.
The present applicant produced, on a trial basis, a semiconductor package 200 shown in FIG. 9 which has the same POP structure as the semiconductor package 100 and studied it to find the following problems.
First, a manufacturing method of the semiconductor package 200 will be outlined. Gold bumps 211 are formed on electrodes of a first semiconductor chip 210 and solder coats 237 are formed on electrodes 232 of a wiring board 230 to which the first semiconductor chip 210 is to be connected. Then, a thermosetting resin film 203 (insulating resin) as typified by NCF (non-conductive film) 203 is bonded to the wiring board 230. Also, an element 203 is not limited to a thermosetting resin film. For example, the element 203 may be an insulating film. Then, the gold bumps 211 of the first semiconductor chip 210 are connected, by thermo-compression bonding, to the solder coats 237 of the wiring board 230 to which the thermosetting resin film 203 is bonded. At this time, the thermosetting resin film 203 is set to a certain extent. Then, the thermosetting resin film 203 is set completely by keeping it at a prescribed temperature for a prescribed time. Finally, a second semiconductor chip 220 is die-bonded to the first semiconductor chip 210.
In the manufacturing method having the above steps of the semiconductor package 200, when the first semiconductor chip 210 is connected to the wiring board 230 by thermo-compression bonding, the thermosetting resin film 203 flows out from the outer periphery of the space between the first semiconductor chip 210 and the wiring board 230 as seen from the photograph of FIG. 7 (taken with the second semiconductor chip 220 removed). The thermosetting resin film 203 has a property that at this time it expands in a concentric manner (circularly) about the center of the film 203 (see FIG. 7).
The following problem was found in this manufacturing step. In a design that the second semiconductor chip 220 overhangs the first semiconductor chip 210 (L: overhang length), that is, in a case that the external size of the second semiconductor chip 220 is larger than that of the first semiconductor chip 210, cavities C tend to be formed under peripheral portions 220a (in particular, corner portions) of the second semiconductor chip 220 during the manufacturing step concerned as shown in the photograph of FIG. 8 (an enlarged version of a corner portion B in FIG. 7) and the schematic sectional view of FIG. 9 (taken perpendicularly to the paper surface of FIG. 7). If such cavities C are formed, the second semiconductor chip 220 may be warped in a step of connecting electrodes (not shown) formed on the top surfaces of the peripheral portions 220a of the second semiconductor chip 220 to electrodes 233 formed on the wiring board 230 by wire bonding, as a result of which their connections may be rendered unstable. Furthermore, in a step of molding the entire structure, a gap may be formed in the interface between the first semiconductor chip 210 and the second semiconductor chip 220 to increase the probability of occurrence of a mold void. These problems are more serious when the overhang length L of the second semiconductor chip 220 is greater.
In view of the above problems, in the conventional technique, it is intended to prevent formation of cavities by reducing the overhang length by using, as part of a base, that portion of the thermosetting resin film which flows out from the space between the first semiconductor chip and the wiring board. However, it is very difficult to stably form a base having a prescribed shape (the shape depends on the amount of resin that flows out) because of variations in process conditions and the dimensions of the members involved. On the other hand, if it is attempted to secure a sufficiently wide base by using a large thermosetting resin film, because of the above-mentioned property that the thermosetting resin film tends to expand in a concentric manner (circularly), an excessive amount of resin flows out from the sidelines, resulting in a problem that wire-bonding electrodes of the wiring board are covered with the expanded portions of the thermosetting resin film.